Conventional memory controllers generally limit power management capabilities to firmware controlled implementations. Such approaches only allow deep, long-term, power reduction modes to be used given the relative slowness of the processor compared to the fast nature of the memory controller. Given the ever increasing need for power reduction, the capabilities of existing buffer controllers are inadequate, leaving a significant potential for power reduction untapped.
Conventional power savings implementations for a DDR system only allow firmware control of a deep-sleep power down mode. Such implementations suspends all buffer activity and places the DDR memory in a self-refresh state to preserve memory content and/or reduce power consumption. Such implementations only work for longer, planned periods of inactivity.
A clock enable (CKE) power-down is a feature specified in the JEDEC standard for DDR memories. However, the JEDEC specified feature only deals with the memory, not how a controller should implement support for this feature (apart from the implication that the controller must meet whatever timing requirements are set out in the JEDEC standard).
Existing power management solutions do not reduce power consumption while the system-on-a-chip is in an active operational state. Existing power management solutions only operate when activity is completely suspended.
It would be desirable to implement hardware controlled power savings control for a memory using an arbiter and/or protocol engine collaboration and/or to dynamically enter and exit a low power state mode during normal operation of the memory.